CSS=SLOW_CLK, PRES=CLOCK
Programmable Clock 0 Register
| CSS | Master Clock Source Selection 0 (SLOW_CLK): Slow Clock is selected 1 (MAIN_CLK): Main Clock is selected 2 (PLLA_CLK): PLLACK/PLLADIV2 is selected 3 (UPLL_CLK): UPLL Clock is selected 4 (MCK_CLK): Master Clock is selected |
| PRES | Programmable Clock Prescaler 0 (CLOCK): Selected clock 1 (CLOCK_DIV2): Selected clock divided by 2 2 (CLOCK_DIV4): Selected clock divided by 4 3 (CLOCK_DIV8): Selected clock divided by 8 4 (CLOCK_DIV16): Selected clock divided by 16 5 (CLOCK_DIV32): Selected clock divided by 32 6 (CLOCK_DIV64): Selected clock divided by 64 |